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  • 权利要求
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    • 专利摘要:
    PURPOSE: A method for correcting a digital error of an analog/digital converter is provided to simplify an error correction process and minimize the power consumption by using a characteristic of a folding signal to divide a region of low bits and correcting errors of high bits according to the divided regions. CONSTITUTION: A low bit coding region is divided into four regions according to an odd number state and an even number state of predicting high bits. A coding process for low bits is performed. A coded result of the low bits is compared with the state of predictive high bits. The sum of the coded low bits and the predicting high bits is outputted if the coded result of the low bits corresponds to the state of predictive high bits. The sum of the coded low bits and the corrected high bits is outputted if the coded result of the low bits does not correspond to the state of predictive high bits.
    公开号:KR20040033596A
    申请号:KR1020020062748
    申请日:2002-10-15
    公开日:2004-04-28
    发明作者:이승철；유현규；김경수；김종대
    申请人:한국전자통신연구원；
    IPC主号:
    专利说明:

    Method of digital error correction of analog-to-digital converter
    [6] The present invention relates to a digital error correction method of an analog-to-digital converter, and more particularly, to a digital error correction method to be used in a low power high speed analog-to-digital converter having a folding structure.
    [7] The conventional digital error correction method of the folding analog-to-digital converter uses a method of differently coding lower bits according to the determination of higher bits and then adding the higher bits together. In this case, the coding method of the lower bit uses a mid-rise type coding.
    [8] 1 is a conceptual diagram illustrating a digital error correction method of a conventional folding analog-to-digital converter.
    [9] Referring to FIG. 1, in the conventional error correction method of a folding analog-to-digital converter, the lower bit is coded differently according to whether the upper bit is odd or even, and the final output corrected by adding the upper bit to the upper bit. Get
    [10] Specifically, the region corresponding to the boundary between '1' and '2' of the upper bit will output the same final code value by calibration even if the upper bit is selected as '1' or '2'. If the upper bit is selected as '1', the lower bit is coded by performing an odd coding method, and when the upper bit is selected as '2', the lower bit is coded by performing an even coding method. As a result, the value of the lower bit to be coded varies according to the state of the upper bit, and when the value is summed with the upper bit, the corrected code value is output.
    [11] For example, in the analog-to-digital converter having the N-bit lower bit of FIG. 1, when the upper bit is determined as '1' or '2' in the M region, the output code is as follows.
    [12] If the upper bit is determined to be '1' in the M region, coding of the lower bit is performed by using a method of 'low bit coding when the upper bit is odd' and 2 N + 1-1 is coded as the lower bit. The final output code is output by multiplying the upper bits by 2 N and then adding the coded lower bits. If this is expressed as an expression, 1 × 2 N + 2 N + 1-1 = 2 N + 1 + 2 N -1.
    [13] On the other hand, if the upper bit is determined to be '2' in the M region, when the upper bit is even when the upper bit is even, using the lower bit coding method, 2 N -1 is coded as the lower bit. Therefore, this expression is expressed as a formula 2 × 2 N + 2 N -1 = 2 N + 1 + 2 N -1. That is, when the upper bits are even and the odd bits are coded so that the lower bits differ by 2 N, the upper bits may be determined as '1' or '2' or the same output may be obtained.
    [14] Detailed description of the above-described error correction method is described in 'An 8-b 100-M Sample / s CMOS Pipelined' published in 'IEEE JSSC VOL.36 No.2' by 'MJchoe, et al' in February 2001. Folding ADC '.
    [15] According to the above technique, when the upper bits are even and the odd bits, two different decoders are required because different coding should be performed on the lower bits, and each decoder requires 2 N for processing N bits of lower bits. This requires a logic circuit that decodes +1 inputs into N + 1 bits. In addition, there is a problem in that the configuration of the system for digital error correction is very difficult by repeating the above-described error correction process when the digital output is obtained in each stage by configuring folding in multiple stages.
    [16] Accordingly, in order to solve the above problem, the present invention divides an area to which a lower bit belongs by using characteristics of a folding signal in an analog-to-digital converter having a folding structure and corrects an error of an upper bit according to each area. Its purpose is to provide a digital error correction method that can simplify calibration and minimize power and area.
    [1] 1 is a conceptual diagram illustrating a digital error correction method of a conventional folding analog-to-digital converter.
    [2] 2 is a conceptual diagram illustrating a digital error correction method of a folding analog-to-digital converter according to the present invention.
    [3] 3A and 3B are conceptual views illustrating a correction method according to a signal generated when an error correction method according to the present invention is applied to an analog-to-digital converter having eight folding signals.
    [4] 4A is a conceptual diagram illustrating error detection of an analog-to-digital converter applying a mid-rise method or a mid-tread method when the expected upper bits are even, and FIG. 4B is a mid-rise when the expected upper bits are odd. It is a conceptual diagram for explaining the error detection of the analog-to-digital converter applying the method or the mid-tread method.
    [5] 5 is a conceptual diagram of applying a digital calibration technique in a mid-tread coding according to the present invention to a folding analog-to-digital converter having a multi-stage structure.
    [17] Defining a lower bit coding region according to the present invention as a total of four regions in which the states of the expected upper bits are two regions for each of odd or even numbers, and the states of the expected upper bits according to the odd or even numbers, respectively. Determining the two defined lower bit coding regions as expected regions, coding the lower bits, and comparing the regions corresponding to the lower bit coding results among the four defined lower bit coding regions. Determining an area, comparing the expected area with the comparison area to perform error detection and correction of the expected upper bits, and using the expected upper bits obtained through the error detection and correction as upper bits, And outputting the sum of the coded lower bits. It provides a digital error correction method.
    [18] Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.
    [19] 2 is a conceptual diagram illustrating a digital error correction method of a folding analog-to-digital converter according to the present invention.
    [20] Referring to FIG. 2, a digital output is performed by dividing 2 N lower bit output values obtained from a folding signal into a predetermined region and adding or subtracting upper bits according to the parity of the corresponding region signal and higher bits for digital error correction of the analog-to-digital converter. Correct it.
    [21] This means that in the folding structure, the information about the actual correct output signal is loaded in the lower bit rather than the upper bit, so if the output of the upper bit outputs a value different from the upper bit value expected in the region to which the lower bit belongs, After correcting the bit value, the upper and lower bits are summed and output.
    [22] Specifically, the lower bits are divided into two equally sized regions according to the expected state of the upper bits (that is, odd or even). Divide the region of the lower bit where an even number of higher bits is expected by 'A' and 'B', and divide the region of the lower bit where an odd number of upper bits are expected by 'C' and 'D'. Separate into areas.
    [23] Next, the correction method of the upper bit will be described.
    [24] If the state of the upper bit expected is even, the coding region of the lower bit should be 'A' or 'B'; otherwise, if the coding region of the lower bit is coded 'C' or 'D', the expected upper It is determined that an error has occurred in the bit, and then, by subtracting or adding 1 to the expected upper bit according to the region of the lower bit, correcting the error and outputting the upper bit. Specifically, when the coding region of the lower bit is 'A', and if the state of the expected upper bit is odd, the error is corrected by adding 1 to the expected upper bit and outputting the upper bit. If the coding region of the lower bit is 'B', and the state of the expected upper bit is odd, the error is corrected by subtracting 1 from the expected upper bit and outputting the upper bit. If the coding region of the lower bit is 'C', and if the expected upper bit state is even, the error is corrected by adding 1 to the upper bit and then outputting the upper bit. If the coding region of the lower bit is 'D', and the state of the expected upper bit is even, the error is corrected by subtracting 1 from the expected upper bit and outputting the upper bit.
    [25] When this is applied to the actual analog-to-digital converter will be described in detail.
    [26] 3A and 3B are conceptual views illustrating a correction method according to a signal generated when an error correction method according to the present invention is applied to an analog-to-digital converter having eight folding signals.
    [27] 2 is applied to an analog-to-digital converter having eight folding signals, as shown in FIG. 3a, the output is output as a shifted value by adding one from the lower 0000001 to 11111111 one by one, and then adding one from 11111110 to 00000000 one by one. The shifted value is output and shows the total number of 16 cases from 00000001 to 00000000. At this time, 00000001 to 00001111 are defined as 'A' area, 00011111 to 11111111 are defined as 'B' area, 1111110 to 11110000 are defined as 'C' area, and 11100000 to 00000000 are defined as 'D' area It is defined as
    [28] In the region classification method, it is possible to determine simply according to the state of two bits of the output of the folding signal. For example, when the most significant bit of the eight folding signal outputs is the first bit, the 4th and 8th bits are observed to distinguish the area. If the output of the 4th and 8th bits is '0' and '1' respectively, the output is 'A' area. If '1' and '1' are output, the 'B' area is '1' and '0'. If it is printed, it is divided into 'C' area, and if it is printed '0' and '0', it is divided into 'D' area. Of course, the present invention is not limited thereto, and the lower bit region may be divided in various ways according to the state of the upper bit. As shown in FIG. 3B, when the most significant bit of the output of FIG. 3A is 1, the actual lower bit is output by inverting the remaining bits, thereby making the outputs of the regions 'A', 'C', 'B' and 'D' equal The decoder can be simplified by having an output value.
    [29] By deriving the area signal from the region to which the lower bit belongs in the above-described method, if the state (parity) of the upper bit is the same as the result expected from the region to which the lower bit belongs, it is determined that there is no error in the upper bit, The lower bit and upper bit are added together and output. If the upper state is different from the result expected from the region to which the lower bit belongs, the upper bit is corrected and the coded lower bit and the corrected upper bit are summed and output.
    [30] As a specific example, if the lower bit has a value of 11111111 (the 'B' region), if there is no error in the upper bit, the state of the upper bit should output an even number. Therefore, if the output of the upper bit is 0 (even), it is determined that there is no error, and the output is added by adding the value of the lower bit, making it an upper bit. If the upper bit has generated an error within the error range of the upper bit, the upper bit will output 1, and as described above, if the lower bit belongs to an `B` area and an odd number occurs, Subtracting 1 from the bit results in a final output of 0, giving you the same output as if there were no errors. Likewise, if the lower bit has a value of 11110000 (the 'C' region), the upper bit should have an odd value if there is no error in the upper bit. Therefore, if the output of the upper bit is 1, it is determined that there is no error. The upper bit is added and the lower bit is added and output. If the upper bit has an error within the error range of the upper bit, the upper bit will output 0. As described above, if the lower bit belongs to the `C` area and the even number occurs, the upper bit is higher. Adding 1 to the bit results in a final output of 1, giving you the same output as if there were no errors. For reference, if the lower bit exists in the `C` area and the upper bit without error is 1, and an error occurs in the upper bit and outputs 2, this is the error range of the correctable upper bit (1/2 of the upper bit). ), Correction of the higher bits becomes impossible.
    [31] The analog-to-digital conversion method of the present invention includes a mid-rise and a mid-tread method. The above-described coding method has been described based on the mid-rise method. Hereinafter, a case in which the mid-tread method is applied to the present invention will be described based on the mid-rise method.
    [32] 4A is a conceptual diagram illustrating error detection of an analog-to-digital converter applying a mid-rise method or a mid-tread method when the expected upper bits are even, and FIG. 4B is a mid-rise when the expected upper bits are odd. It is a conceptual diagram for explaining the error detection of the analog-to-digital converter applying the method or the mid-tread method.
    [33] Referring to FIG. 4A, the mid-rise method outputs an upper bit as an upper bit when an area to which a lower bit belongs is 'A' or 'B' when an upper bit is an even number. If the region to which the lower bit belongs is the 'C' region, the correction is performed by adding 1 to the upper bit and outputting the upper bit. In addition, if the region to which the lower bit belongs is a 'D' region, the correction is performed by subtracting 1 from the upper bit and outputting the upper bit.
    [34] On the other hand, the mid-tread method outputs the expected upper bit without correction if the lower bit belongs to the 'A' or 'B' area when the upper bit is even, and if the region to which the lower bit belongs is 'C' or In the 'D' area, the correction is made by subtracting 1 from the upper bit and outputting it as the upper bit.
    [35] Specifically, if the output value of the upper bit is' 2 'and the region to which the lower bit belongs is the' A 'or' B` region through the mid-tread method, '2' is replaced by the lower bit without correction of the upper bit. Sum up and print. Comparing this with the mid-rise correction, if the low-bit is `A` or` B`, the high-order bit and the low-order bit are output without changing the high-order bit, so the two methods show the same output. have. If the region to which the lower bit belongs is determined to be the 'C' or 'D' region, the mid-tread method subtracts 1 from the upper bit, performs upper bit correction, and then outputs '1' as the upper bit, as shown in FIG. 4A. It has the same output as when using the mid-rise method.
    [36] Referring to FIG. 4B, the mid-rise method outputs an upper bit as an upper bit when the coding region of the lower bit is 'C' or 'D' when the upper bit is odd. If the coding region of the lower bit is an 'A' region, the correction is performed by adding 1 to the upper bit and outputting the upper bit. If the lower bit coding area is the 'B' area, the correction is performed by subtracting 1 from the upper bit and outputting the upper bit.
    [37] On the other hand, the mid-tread method outputs the upper bit as the upper bit when the coding region of the lower bit is 'C' or 'D' when the upper bit is odd, and if the coding region of the lower bit is 'A' or 'B'. If it is an area, the correction is made by subtracting 1 from the upper bit and outputting it as the upper bit.
    [38] Specifically, if the output value of the upper bit is '1' and the coding region of the lower bit is the 'C' or 'D' region through the mid-tread method, '1' is output as the upper bit without correction of the upper bit. However, if the 'A' or 'B' region is selected as the lower bit coding region, the upper bit correction is performed by subtracting 1 from the expected upper bit and then outputting '0' as the upper bit. Get the output.
    [39] Thus, when the mid-tread method is selected, the area where the expected high bit value is not converted is set to A ', and the area for correcting the error of the expected high bit is defined as B' so that only two areas can be identified. Calibration can be made simpler in hardware.
    [40] In addition, the digital error correction in the analog-to-digital converter of the multi-stage folding structure can be performed by using the digital error correction method in the mid-rise coding and the digital correction method in the mid-tread coding in succession, or depending on the advantages and disadvantages of the hardware implementation. It is possible to use a mixture of methods, and when using the calibration technique of the present invention, it is the simplest to implement a calibrator when mid-tread coding is applied continuously.
    [41] 5 is a conceptual diagram of applying a digital calibration technique in a mid-tread coding according to the present invention to a folding analog-to-digital converter having a multi-stage structure.
    [42] Referring to FIG. 5, the correction of the error is made from the lower bits to the higher bits, and the correction method is performed by repeating the proposed mid-tread coding scheme. For example, if the region where the lower bit belongs is A '' and the parity of the middle bit before correction is 1, the corrected intermediate bit value is subtracted from the value before correction by 1, and thus the corrected intermediate bit output The upper bit is corrected again.
    [43] Specifically, when the least significant bit of the middle bit is 1, if the lower bit belongs to the A '' region, 1 is subtracted from the middle bit, and if the lower bit belongs to the B '' region, the middle bit is output as it is. If the least significant bit of the middle bit is 0, if the lower bit belongs to A '' area, the middle bit is output as it is; if the lower bit belongs to B '' area, 1 is subtracted from the middle bit. In this way, the intermediate bit output is corrected and then the upper bit is corrected. When the least significant bit of the upper bit is 1, if the corrected middle bit belongs to the A 'region, the subtracting 1 is output from the upper bit, and if the corrected middle bit belongs to the B' region, the upper bit is output as it is. When the least significant bit of the upper bit is 0, if the corrected middle bit belongs to the A 'region, the upper bit is output as it is, and if the corrected middle bit belongs to the B' region, 1 is subtracted from the upper bit. This can reduce the complexity of conventional multi-stage analog-digital calibrator.
    [44] In addition, the digital error correction method of the present invention uses a logic circuit that decodes 2 N inputs into N bits in order to obtain a low bit output of N bits by performing coding in the form of mid-rise or mid-tread.
    [45] As described above, the present invention can simplify the structure of the digital calibrator by using the digital error correction method of the analog-to-digital converter, reduce the complexity of the low-bit decoder in half, and reduce the power consumption and area of the calibrator and the decoder. Can be minimized.
    [46] In addition, the digital error correction method of the analog-to-digital converter is applicable to both the mid-rise and mid-tread coding, so that the hardware can be implemented as the coding method most suitable for the analog-to-digital conversion.
    [47] In addition, the digital error correction method of the present invention can be easily applied to digital calibration of a multi-stage folding structure.
    权利要求:
    Claims (5)
    [1" claim-type="Currently amended] (a) defining the lower bit coding regions into four regions of two regions according to the states of odd or even numbers of the upper bits expected;
    (b) coding the lower bits;
    (c) determining whether the lower bit coding result matches the expected state of the upper bit;
    (d) summing and outputting the coded lower bits and the expected upper bits if they match, and correcting the expected upper bits and outputting the sums with the coded lower bits if they do not match. Error correction method for analog-to-digital converter.
    [2" claim-type="Currently amended] The method of claim 1, wherein step (a) comprises:
    Extracting 2 bits from the lower bit coding result, and defining the lower bit coding result of values having the same logic state as the two bits as one region.
    [3" claim-type="Currently amended] The method of claim 1, wherein the lower bit coding is a mid-rise coding scheme or a mid-tread coding scheme.
    [4" claim-type="Currently amended] The method of claim 3, wherein when the coding of the lower bit is a mid-rise type coding scheme, when the lower bit coding result does not match the state of the expected upper bit, 1 is added to or subtracted from the expected upper bit. And correcting the expected higher bits.
    [5" claim-type="Currently amended] 4. The method of claim 3, wherein when the coding of the lower bit is a mid-tread type coding scheme, subtracting 1 from the expected upper bit when the lower bit coding result does not match a state of the expected upper bit. A digital error correction method for an analog-to-digital converter, characterized by correcting expected high bits.
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    同族专利:
    公开号 | 公开日
    KR100460700B1|2004-12-09|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2002-10-15|Application filed by 한국전자통신연구원
    2002-10-15|Priority to KR10-2002-0062748A
    2004-04-28|Publication of KR20040033596A
    2004-12-09|Application granted
    2004-12-09|Publication of KR100460700B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR10-2002-0062748A|KR100460700B1|2002-10-15|2002-10-15|Method of digital error correction of analog-to-digital converter|
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